Taiyo Holdings Launches Next-generation Semiconductor-packaging Material "FPIM Series," Achieving Its First Three-layer RDL Formation with 700-nm CD on 12-inch Wafers

Taiyo Holdings presented new progress on its “FPIM Series” semiconductor-packaging material, targeting finer wiring for advanced packaging. The company, based in Tokyo, shared results on Sept. 10, 2026 at the 11th IEEE Electronics System-Integration Technology Conference (IEEE ESTC 2026) in Helsinki, Finland. Co-authored with imec, the research describes FPIM as a fine-pitch RDL negative-tone i-line photosensitive insulating material for dual damascene processes. Taiyo and imec formed a three-layer RDL structure on 12-inch wafers and achieved a 700-nm critical dimension for both interconnects and vias. Metal 1 showed favorable leakage current and resistance, and the material was confirmed suitable for CMP. Taiyo plans to target 500 nm or less and continued reliability verification, while shipping small-volume R&D samples in 2025.